library verilog;
use verilog.vl_types.all;
entity pan is
    port(
        clk             : in     vl_logic;
        start           : in     vl_logic;
        left            : in     vl_logic;
        right           : in     vl_logic;
        brake           : in     vl_logic;
        stop            : in     vl_logic;
        LR              : out    vl_logic_vector(9 downto 0)
    );
end pan;
